.stabs "E:\\cmh_com_infor\\105.m68_code\\m68_2_chanl\\Lib\\",0x64,0,0,0
.stabs "E:\\cmh_com_infor\\105.m68_code\\m68_2_chanl\\Lib\\SysRegDefine.c",0x64,0,0,0
.stabs "int:t1=r1;-32768;32767;",0x80,0,0,0
.stabs "unsigned int:t2=r2;0;65535;",0x80,0,0,0
.stabs "long int:t3=r3;-2147483648;2147483647;",0x80,0,0,0
.stabs "unsigned long int:t4=r4;0;4294967295;",0x80,0,0,0
.stabs "long long unsigned int:t6=r6;0;4294967295;",0x80,0,0,0
.stabs "short int:t7=r7;-32768;32767;",0x80,0,0,0
.stabs "short unsigned int:t8=r8;0;65535;",0x80,0,0,0
.stabs "char:t9=r9;-128;127;",0x80,0,0,0
.stabs "unsigned char:t10=r10;0;255;",0x80,0,0,0
.stabs "_Bool:t11=r11;0;1;",0x80,0,0,0
.stabs "sbit:t12=r12;0;1;",0x80,0,0,0
.stabs "float:t13=r13;4;0;",0x80,0,0,0
.stabs "double:t14=r14;4;0;",0x80,0,0,0
.stabs "long double:t15=r15;4;0;",0x80,0,0,0
.stabs "void:t16=r10;0;255;",0x80,0,0,0
.stabs "IND0:G10;",0x20,0,0,_IND0
.stabs "IND1:G10;",0x20,0,0,_IND1
.stabs "FSR0:G10;",0x20,0,0,_FSR0
.stabs "FSR1:G10;",0x20,0,0,_FSR1
.stabs "STATUS:G10;",0x20,0,0,_STATUS
.stabs "WORK:G10;",0x20,0,0,_WORK
.stabs "INTF:G10;",0x20,0,0,_INTF
.stabs "INTE:G10;",0x20,0,0,_INTE
.stabs "BSR:G10;",0x20,0,0,_BSR
.stabs "MCK:G10;",0x20,0,0,_MCK
.stabs "EADRH:G10;",0x20,0,0,_EADRH
.stabs "EADRL:G10;",0x20,0,0,_EADRL
.stabs "EDAT:G10;",0x20,0,0,_EDAT
.stabs "EOPEN:G10;",0x20,0,0,_EOPEN
.stabs "WDTCON:G10;",0x20,0,0,_WDTCON
.stabs "WDTIN:G10;",0x20,0,0,_WDTIN
.stabs "ADOH:G10;",0x20,0,0,_ADOH
.stabs "ROOT:G10;",0x20,0,0,_ROOT
.stabs "RSTSR:G10;",0x20,0,0,_RSTSR
.stabs "ADCFG:G10;",0x20,0,0,_ADCFG
.stabs "ANACFG:G10;",0x20,0,0,_ANACFG
.stabs "LVDCON:G10;",0x20,0,0,_LVDCON
.stabs "ADOL:G10;",0x20,0,0,_ADOL
.stabs "PT1:G10;",0x20,0,0,_PT1
.stabs "PT1EN:G10;",0x20,0,0,_PT1EN
.stabs "PT1PU:G10;",0x20,0,0,_PT1PU
.stabs "INPUT:G10;",0x20,0,0,_INPUT
.stabs "PTCON:G10;",0x20,0,0,_PTCON
.stabs "PTINT0:G10;",0x20,0,0,_PTINT0
.stabs "PTINT1:G10;",0x20,0,0,_PTINT1
.stabs "TM0CON:G10;",0x20,0,0,_TM0CON
.stabs "TM0IN:G10;",0x20,0,0,_TM0IN
.stabs "TM0CNT:G10;",0x20,0,0,_TM0CNT
.stabs "TM1CON:G10;",0x20,0,0,_TM1CON
.stabs "TM1IN:G10;",0x20,0,0,_TM1IN
.stabs "TM1CNT:G10;",0x20,0,0,_TM1CNT
.stabs "INTF3:G10;",0x20,0,0,_INTF3
.stabs "INTE3:G10;",0x20,0,0,_INTE3
.stabs "I2CCON:G10;",0x20,0,0,_I2CCON
.stabs "I2CDAT:G10;",0x20,0,0,_I2CDAT
.stabs "I2CISR:G10;",0x20,0,0,_I2CISR
.stabs "ADCON:G10;",0x20,0,0,_ADCON
.stabs "WDT_TRIM:G10;",0x20,0,0,_WDT_TRIM
.stabs "ICK_TRIM:G10;",0x20,0,0,_ICK_TRIM
.stabs "VS_TRIM:G10;",0x20,0,0,_VS_TRIM
.stabs "METCH:G10;",0x20,0,0,_METCH
.stabs "I2CADR:G10;",0x20,0,0,_I2CADR
.stabs "Z:G12;",0x20,0,0,_Z
.stabs "C:G12;",0x20,0,0,_C
.stabs "DC:G12;",0x20,0,0,_DC
.stabs "TO:G12;",0x20,0,0,_TO
.stabs "PD:G12;",0x20,0,0,_PD
.stabs "E0IF:G12;",0x20,0,0,_E0IF
.stabs "E1IF:G12;",0x20,0,0,_E1IF
.stabs "ADIF:G12;",0x20,0,0,_ADIF
.stabs "TM0IF:G12;",0x20,0,0,_TM0IF
.stabs "TM1IF:G12;",0x20,0,0,_TM1IF
.stabs "E0IE:G12;",0x20,0,0,_E0IE
.stabs "E1IE:G12;",0x20,0,0,_E1IE
.stabs "ADIE:G12;",0x20,0,0,_ADIE
.stabs "TM0IE:G12;",0x20,0,0,_TM0IE
.stabs "TM1IE:G12;",0x20,0,0,_TM1IE
.stabs "GIE:G12;",0x20,0,0,_GIE
.stabs "PAGE0:G12;",0x20,0,0,_PAGE0
.stabs "PAGE1:G12;",0x20,0,0,_PAGE1
.stabs "IRP1:G12;",0x20,0,0,_IRP1
.stabs "IRP0:G12;",0x20,0,0,_IRP0
.stabs "WDT_CLK_EN:G12;",0x20,0,0,_WDT_CLK_EN
.stabs "M3_CK:G12;",0x20,0,0,_M3_CK
.stabs "PARH_0:G12;",0x20,0,0,_PARH_0
.stabs "PARH_1:G12;",0x20,0,0,_PARH_1
.stabs "PARH_2:G12;",0x20,0,0,_PARH_2
.stabs "PARH_3:G12;",0x20,0,0,_PARH_3
.stabs "PARH_4:G12;",0x20,0,0,_PARH_4
.stabs "PARH_5:G12;",0x20,0,0,_PARH_5
.stabs "READ_CHECK:G12;",0x20,0,0,_READ_CHECK
.stabs "PROG_BUSY:G12;",0x20,0,0,_PROG_BUSY
.stabs "PARL_0:G12;",0x20,0,0,_PARL_0
.stabs "PARL_1:G12;",0x20,0,0,_PARL_1
.stabs "PARL_2:G12;",0x20,0,0,_PARL_2
.stabs "PARL_3:G12;",0x20,0,0,_PARL_3
.stabs "PARL_4:G12;",0x20,0,0,_PARL_4
.stabs "PARL_5:G12;",0x20,0,0,_PARL_5
.stabs "PARL_6:G12;",0x20,0,0,_PARL_6
.stabs "PARL_7:G12;",0x20,0,0,_PARL_7
.stabs "EDAT_0:G12;",0x20,0,0,_EDAT_0
.stabs "EDAT_1:G12;",0x20,0,0,_EDAT_1
.stabs "EDAT_2:G12;",0x20,0,0,_EDAT_2
.stabs "EDAT_3:G12;",0x20,0,0,_EDAT_3
.stabs "EDAT_4:G12;",0x20,0,0,_EDAT_4
.stabs "EDAT_5:G12;",0x20,0,0,_EDAT_5
.stabs "EDAT_6:G12;",0x20,0,0,_EDAT_6
.stabs "EDAT_7:G12;",0x20,0,0,_EDAT_7
.stabs "EOPEN_0:G12;",0x20,0,0,_EOPEN_0
.stabs "EOPEN_1:G12;",0x20,0,0,_EOPEN_1
.stabs "EOPEN_2:G12;",0x20,0,0,_EOPEN_2
.stabs "EOPEN_3:G12;",0x20,0,0,_EOPEN_3
.stabs "EOPEN_4:G12;",0x20,0,0,_EOPEN_4
.stabs "EOPEN_5:G12;",0x20,0,0,_EOPEN_5
.stabs "EOPEN_6:G12;",0x20,0,0,_EOPEN_6
.stabs "EOPEN_7:G12;",0x20,0,0,_EOPEN_7
.stabs "WDTS_0:G12;",0x20,0,0,_WDTS_0
.stabs "WDTS_1:G12;",0x20,0,0,_WDTS_1
.stabs "WDTS_2:G12;",0x20,0,0,_WDTS_2
.stabs "I2C_DIV_0:G12;",0x20,0,0,_I2C_DIV_0
.stabs "I2C_DIV_1:G12;",0x20,0,0,_I2C_DIV_1
.stabs "ROOT_EN:G12;",0x20,0,0,_ROOT_EN
.stabs "WDTEN:G12;",0x20,0,0,_WDTEN
.stabs "WDTIN_0:G12;",0x20,0,0,_WDTIN_0
.stabs "WDTIN_1:G12;",0x20,0,0,_WDTIN_1
.stabs "WDTIN_2:G12;",0x20,0,0,_WDTIN_2
.stabs "WDTIN_3:G12;",0x20,0,0,_WDTIN_3
.stabs "WDTIN_4:G12;",0x20,0,0,_WDTIN_4
.stabs "WDTIN_5:G12;",0x20,0,0,_WDTIN_5
.stabs "WDTIN_6:G12;",0x20,0,0,_WDTIN_6
.stabs "WDTIN_7:G12;",0x20,0,0,_WDTIN_7
.stabs "ADO_8:G12;",0x20,0,0,_ADO_8
.stabs "ADO_9:G12;",0x20,0,0,_ADO_9
.stabs "ADO_10:G12;",0x20,0,0,_ADO_10
.stabs "ADO_11:G12;",0x20,0,0,_ADO_11
.stabs "ADO_12:G12;",0x20,0,0,_ADO_12
.stabs "ADO_13:G12;",0x20,0,0,_ADO_13
.stabs "ADO_14:G12;",0x20,0,0,_ADO_14
.stabs "ADO_15:G12;",0x20,0,0,_ADO_15
.stabs "ROOT_0:G12;",0x20,0,0,_ROOT_0
.stabs "ROOT_1:G12;",0x20,0,0,_ROOT_1
.stabs "ROOT_2:G12;",0x20,0,0,_ROOT_2
.stabs "ROOT_3:G12;",0x20,0,0,_ROOT_3
.stabs "ROOT_4:G12;",0x20,0,0,_ROOT_4
.stabs "ROOT_5:G12;",0x20,0,0,_ROOT_5
.stabs "ROOT_6:G12;",0x20,0,0,_ROOT_6
.stabs "ROOT_7:G12;",0x20,0,0,_ROOT_7
.stabs "ILOPF:G12;",0x20,0,0,_ILOPF
.stabs "EMCF:G12;",0x20,0,0,_EMCF
.stabs "LVDF:G12;",0x20,0,0,_LVDF
.stabs "CHOPM_0:G12;",0x20,0,0,_CHOPM_0
.stabs "CHOPM_1:G12;",0x20,0,0,_CHOPM_1
.stabs "S_GAIN_0:G12;",0x20,0,0,_S_GAIN_0
.stabs "S_GAIN_1:G12;",0x20,0,0,_S_GAIN_1
.stabs "ADSC:G12;",0x20,0,0,_ADSC
.stabs "ADEN:G12;",0x20,0,0,_ADEN
.stabs "SINL_0:G12;",0x20,0,0,_SINL_0
.stabs "SINL_1:G12;",0x20,0,0,_SINL_1
.stabs "BGID:G12;",0x20,0,0,_BGID
.stabs "BGR_ENB:G12;",0x20,0,0,_BGR_ENB
.stabs "LDOS_0:G12;",0x20,0,0,_LDOS_0
.stabs "LDOS_1:G12;",0x20,0,0,_LDOS_1
.stabs "LDOEN:G12;",0x20,0,0,_LDOEN
.stabs "LB_RST_CON:G12;",0x20,0,0,_LB_RST_CON
.stabs "LBOUT:G12;",0x20,0,0,_LBOUT
.stabs "SILB_0:G12;",0x20,0,0,_SILB_0
.stabs "SILB_1:G12;",0x20,0,0,_SILB_1
.stabs "SILB_2:G12;",0x20,0,0,_SILB_2
.stabs "AIENB1:G12;",0x20,0,0,_AIENB1
.stabs "LVDEN:G12;",0x20,0,0,_LVDEN
.stabs "ADO_0:G12;",0x20,0,0,_ADO_0
.stabs "ADO_1:G12;",0x20,0,0,_ADO_1
.stabs "ADO_2:G12;",0x20,0,0,_ADO_2
.stabs "ADO_3:G12;",0x20,0,0,_ADO_3
.stabs "ADO_4:G12;",0x20,0,0,_ADO_4
.stabs "ADO_5:G12;",0x20,0,0,_ADO_5
.stabs "ADO_6:G12;",0x20,0,0,_ADO_6
.stabs "ADO_7:G12;",0x20,0,0,_ADO_7
.stabs "PT1_0:G12;",0x20,0,0,_PT1_0
.stabs "PT1_1:G12;",0x20,0,0,_PT1_1
.stabs "PT1_2:G12;",0x20,0,0,_PT1_2
.stabs "PT1_3:G12;",0x20,0,0,_PT1_3
.stabs "PT1_4:G12;",0x20,0,0,_PT1_4
.stabs "PT1_5:G12;",0x20,0,0,_PT1_5
.stabs "PT1EN_0:G12;",0x20,0,0,_PT1EN_0
.stabs "PT1EN_1:G12;",0x20,0,0,_PT1EN_1
.stabs "PT1EN_2:G12;",0x20,0,0,_PT1EN_2
.stabs "PT1EN_3:G12;",0x20,0,0,_PT1EN_3
.stabs "PT1EN_4:G12;",0x20,0,0,_PT1EN_4
.stabs "PT1EN_5:G12;",0x20,0,0,_PT1EN_5
.stabs "PT1UP_0:G12;",0x20,0,0,_PT1UP_0
.stabs "PT1UP_1:G12;",0x20,0,0,_PT1UP_1
.stabs "PT10_OD:G12;",0x20,0,0,_PT10_OD
.stabs "PT11_OD:G12;",0x20,0,0,_PT11_OD
.stabs "I2C_FLT:G12;",0x20,0,0,_I2C_FLT
.stabs "PT10_VDD:G12;",0x20,0,0,_PT10_VDD
.stabs "PT11_VDD:G12;",0x20,0,0,_PT11_VDD
.stabs "I2C_VDD:G12;",0x20,0,0,_I2C_VDD
.stabs "PT14_VDD:G12;",0x20,0,0,_PT14_VDD
.stabs "PT15_VDD:G12;",0x20,0,0,_PT15_VDD
.stabs "E0M_0:G12;",0x20,0,0,_E0M_0
.stabs "E0M_1:G12;",0x20,0,0,_E0M_1
.stabs "E1M_0:G12;",0x20,0,0,_E1M_0
.stabs "E1M_1:G12;",0x20,0,0,_E1M_1
.stabs "PTW0_0:G12;",0x20,0,0,_PTW0_0
.stabs "PTW0_1:G12;",0x20,0,0,_PTW0_1
.stabs "PTW0_2:G12;",0x20,0,0,_PTW0_2
.stabs "PTW1_0:G12;",0x20,0,0,_PTW1_0
.stabs "PTW1_1:G12;",0x20,0,0,_PTW1_1
.stabs "PTW1_2:G12;",0x20,0,0,_PTW1_2
.stabs "T0SEL:G12;",0x20,0,0,_T0SEL
.stabs "T0RSTB:G12;",0x20,0,0,_T0RSTB
.stabs "T0RATE_0:G12;",0x20,0,0,_T0RATE_0
.stabs "T0RATE_1:G12;",0x20,0,0,_T0RATE_1
.stabs "T0RATE_2:G12;",0x20,0,0,_T0RATE_2
.stabs "T0EN:G12;",0x20,0,0,_T0EN
.stabs "TM0IN_0:G12;",0x20,0,0,_TM0IN_0
.stabs "TM0IN_1:G12;",0x20,0,0,_TM0IN_1
.stabs "TM0IN_2:G12;",0x20,0,0,_TM0IN_2
.stabs "TM0IN_3:G12;",0x20,0,0,_TM0IN_3
.stabs "TM0IN_4:G12;",0x20,0,0,_TM0IN_4
.stabs "TM0IN_5:G12;",0x20,0,0,_TM0IN_5
.stabs "TM0IN_6:G12;",0x20,0,0,_TM0IN_6
.stabs "TM0IN_7:G12;",0x20,0,0,_TM0IN_7
.stabs "TM0CNT_0:G12;",0x20,0,0,_TM0CNT_0
.stabs "TM0CNT_1:G12;",0x20,0,0,_TM0CNT_1
.stabs "TM0CNT_2:G12;",0x20,0,0,_TM0CNT_2
.stabs "TM0CNT_3:G12;",0x20,0,0,_TM0CNT_3
.stabs "TM0CNT_4:G12;",0x20,0,0,_TM0CNT_4
.stabs "TM0CNT_5:G12;",0x20,0,0,_TM0CNT_5
.stabs "TM0CNT_6:G12;",0x20,0,0,_TM0CNT_6
.stabs "TM0CNT_7:G12;",0x20,0,0,_TM0CNT_7
.stabs "T1SEL:G12;",0x20,0,0,_T1SEL
.stabs "T1RSTB:G12;",0x20,0,0,_T1RSTB
.stabs "T1RATE_0:G12;",0x20,0,0,_T1RATE_0
.stabs "T1RATE_1:G12;",0x20,0,0,_T1RATE_1
.stabs "T1RATE_2:G12;",0x20,0,0,_T1RATE_2
.stabs "T1EN:G12;",0x20,0,0,_T1EN
.stabs "TM1IN_0:G12;",0x20,0,0,_TM1IN_0
.stabs "TM1IN_1:G12;",0x20,0,0,_TM1IN_1
.stabs "TM1IN_2:G12;",0x20,0,0,_TM1IN_2
.stabs "TM1IN_3:G12;",0x20,0,0,_TM1IN_3
.stabs "TM1IN_4:G12;",0x20,0,0,_TM1IN_4
.stabs "TM1IN_5:G12;",0x20,0,0,_TM1IN_5
.stabs "TM1IN_6:G12;",0x20,0,0,_TM1IN_6
.stabs "TM1IN_7:G12;",0x20,0,0,_TM1IN_7
.stabs "TM1CNT_0:G12;",0x20,0,0,_TM1CNT_0
.stabs "TM1CNT_1:G12;",0x20,0,0,_TM1CNT_1
.stabs "TM1CNT_2:G12;",0x20,0,0,_TM1CNT_2
.stabs "TM1CNT_3:G12;",0x20,0,0,_TM1CNT_3
.stabs "TM1CNT_4:G12;",0x20,0,0,_TM1CNT_4
.stabs "TM1CNT_5:G12;",0x20,0,0,_TM1CNT_5
.stabs "TM1CNT_6:G12;",0x20,0,0,_TM1CNT_6
.stabs "TM1CNT_7:G12;",0x20,0,0,_TM1CNT_7
.stabs "I2C_STIF:G12;",0x20,0,0,_I2C_STIF
.stabs "I2C_RIF:G12;",0x20,0,0,_I2C_RIF
.stabs "I2C_TIF:G12;",0x20,0,0,_I2C_TIF
.stabs "I2C_STIE:G12;",0x20,0,0,_I2C_STIE
.stabs "I2C_RIE:G12;",0x20,0,0,_I2C_RIE
.stabs "I2C_TIE:G12;",0x20,0,0,_I2C_TIE
.stabs "I2CSTUS_0:G12;",0x20,0,0,_I2CSTUS_0
.stabs "I2CSTUS_1:G12;",0x20,0,0,_I2CSTUS_1
.stabs "I2CSTUS_2:G12;",0x20,0,0,_I2CSTUS_2
.stabs "I2CSTUS_3:G12;",0x20,0,0,_I2CSTUS_3
.stabs "ACK_EN:G12;",0x20,0,0,_ACK_EN
.stabs "CST_EN:G12;",0x20,0,0,_CST_EN
.stabs "AWK_EN:G12;",0x20,0,0,_AWK_EN
.stabs "I2C_EN:G12;",0x20,0,0,_I2C_EN
.stabs "I2CDAT_0:G12;",0x20,0,0,_I2CDAT_0
.stabs "I2CDAT_1:G12;",0x20,0,0,_I2CDAT_1
.stabs "I2CDAT_2:G12;",0x20,0,0,_I2CDAT_2
.stabs "I2CDAT_3:G12;",0x20,0,0,_I2CDAT_3
.stabs "I2CDAT_4:G12;",0x20,0,0,_I2CDAT_4
.stabs "I2CDAT_5:G12;",0x20,0,0,_I2CDAT_5
.stabs "I2CDAT_6:G12;",0x20,0,0,_I2CDAT_6
.stabs "I2CDAT_7:G12;",0x20,0,0,_I2CDAT_7
.stabs "TXE:G12;",0x20,0,0,_TXE
.stabs "ADM_0:G12;",0x20,0,0,_ADM_0
.stabs "ADM_1:G12;",0x20,0,0,_ADM_1
.stabs "AINOUT_0:G12;",0x20,0,0,_AINOUT_0
.stabs "AINOUT_1:G12;",0x20,0,0,_AINOUT_1
.stabs "VS_LIMIT:G12;",0x20,0,0,_VS_LIMIT
.stabs "VS0_OEN:G12;",0x20,0,0,_VS0_OEN
.stabs "WDT_TRIM_0:G12;",0x20,0,0,_WDT_TRIM_0
.stabs "WDT_TRIM_1:G12;",0x20,0,0,_WDT_TRIM_1
.stabs "WDT_TRIM_2:G12;",0x20,0,0,_WDT_TRIM_2
.stabs "WDT_TRIM_3:G12;",0x20,0,0,_WDT_TRIM_3
.stabs "TMOD_0:G12;",0x20,0,0,_TMOD_0
.stabs "TMOD_1:G12;",0x20,0,0,_TMOD_1
.stabs "ICK_TRIM_0:G12;",0x20,0,0,_ICK_TRIM_0
.stabs "ICK_TRIM_1:G12;",0x20,0,0,_ICK_TRIM_1
.stabs "ICK_TRIM_2:G12;",0x20,0,0,_ICK_TRIM_2
.stabs "ICK_TRIM_3:G12;",0x20,0,0,_ICK_TRIM_3
.stabs "ICK_TRIM_4:G12;",0x20,0,0,_ICK_TRIM_4
.stabs "ICK_TRIM_5:G12;",0x20,0,0,_ICK_TRIM_5
.stabs "ICK_TRIM_6:G12;",0x20,0,0,_ICK_TRIM_6
.stabs "ICK_TRIM_7:G12;",0x20,0,0,_ICK_TRIM_7
.stabs "VS_TRIM_0:G12;",0x20,0,0,_VS_TRIM_0
.stabs "VS_TRIM_1:G12;",0x20,0,0,_VS_TRIM_1
.stabs "VS_TRIM_2:G12;",0x20,0,0,_VS_TRIM_2
.stabs "VS_TRIM_3:G12;",0x20,0,0,_VS_TRIM_3
.stabs "LVD_TRIM_0:G12;",0x20,0,0,_LVD_TRIM_0
.stabs "LVD_TRIM_1:G12;",0x20,0,0,_LVD_TRIM_1
.stabs "LVD_TRIM_2:G12;",0x20,0,0,_LVD_TRIM_2
.stabs "SIM_RST:G12;",0x20,0,0,_SIM_RST
.stabs "EVPP_EN:G12;",0x20,0,0,_EVPP_EN
.stabs "METCH_0:G12;",0x20,0,0,_METCH_0
.stabs "METCH_1:G12;",0x20,0,0,_METCH_1
.stabs "METCH_2:G12;",0x20,0,0,_METCH_2
.stabs "METCH_3:G12;",0x20,0,0,_METCH_3
.stabs "GC_EN:G12;",0x20,0,0,_GC_EN
.stabs "I2CADR_0:G12;",0x20,0,0,_I2CADR_0
.stabs "I2CADR_1:G12;",0x20,0,0,_I2CADR_1
.stabs "I2CADR_2:G12;",0x20,0,0,_I2CADR_2
.stabs "I2CADR_3:G12;",0x20,0,0,_I2CADR_3
.stabs "I2CADR_4:G12;",0x20,0,0,_I2CADR_4
.stabs "I2CADR_5:G12;",0x20,0,0,_I2CADR_5
.stabs "I2CADR_6:G12;",0x20,0,0,_I2CADR_6
.include "csccCond.inc"
.include "csccCmp.inc"
.include "csccShift.inc"
	_IND0_SysRegDefine.c .section bank0,addr=0
	_IND0 .ds 1
	.ends
	_IND1_SysRegDefine.c .section bank0,addr=1
	_IND1 .ds 1
	.ends
	_FSR0_SysRegDefine.c .section bank0,addr=2
	_FSR0 .ds 1
	.ends
	_FSR1_SysRegDefine.c .section bank0,addr=3
	_FSR1 .ds 1
	.ends
	_STATUS_SysRegDefine.c .section bank0,addr=4
	_STATUS .ds 1
	.ends
	_WORK_SysRegDefine.c .section bank0,addr=5
	_WORK .ds 1
	.ends
	_INTF_SysRegDefine.c .section bank0,addr=6
	_INTF .ds 1
	.ends
	_INTE_SysRegDefine.c .section bank0,addr=7
	_INTE .ds 1
	.ends
	_BSR_SysRegDefine.c .section bank0,addr=8
	_BSR .ds 1
	.ends
	_MCK_SysRegDefine.c .section bank0,addr=9
	_MCK .ds 1
	.ends
	_EADRH_SysRegDefine.c .section bank0,addr=10
	_EADRH .ds 1
	.ends
	_EADRL_SysRegDefine.c .section bank0,addr=11
	_EADRL .ds 1
	.ends
	_EDAT_SysRegDefine.c .section bank0,addr=12
	_EDAT .ds 1
	.ends
	_EOPEN_SysRegDefine.c .section bank0,addr=13
	_EOPEN .ds 1
	.ends
	_WDTCON_SysRegDefine.c .section bank0,addr=14
	_WDTCON .ds 1
	.ends
	_WDTIN_SysRegDefine.c .section bank0,addr=15
	_WDTIN .ds 1
	.ends
	_ADOH_SysRegDefine.c .section bank0,addr=17
	_ADOH .ds 1
	.ends
	_ROOT_SysRegDefine.c .section bank0,addr=19
	_ROOT .ds 1
	.ends
	_RSTSR_SysRegDefine.c .section bank0,addr=20
	_RSTSR .ds 1
	.ends
	_ADCFG_SysRegDefine.c .section bank0,addr=22
	_ADCFG .ds 1
	.ends
	_ANACFG_SysRegDefine.c .section bank0,addr=23
	_ANACFG .ds 1
	.ends
	_LVDCON_SysRegDefine.c .section bank0,addr=27
	_LVDCON .ds 1
	.ends
	_ADOL_SysRegDefine.c .section bank0,addr=28
	_ADOL .ds 1
	.ends
	_PT1_SysRegDefine.c .section bank0,addr=29
	_PT1 .ds 1
	.ends
	_PT1EN_SysRegDefine.c .section bank0,addr=30
	_PT1EN .ds 1
	.ends
	_PT1PU_SysRegDefine.c .section bank0,addr=31
	_PT1PU .ds 1
	.ends
	_INPUT_SysRegDefine.c .section bank0,addr=44
	_INPUT .ds 1
	.ends
	_PTCON_SysRegDefine.c .section bank0,addr=45
	_PTCON .ds 1
	.ends
	_PTINT0_SysRegDefine.c .section bank0,addr=46
	_PTINT0 .ds 1
	.ends
	_PTINT1_SysRegDefine.c .section bank0,addr=47
	_PTINT1 .ds 1
	.ends
	_TM0CON_SysRegDefine.c .section bank0,addr=52
	_TM0CON .ds 1
	.ends
	_TM0IN_SysRegDefine.c .section bank0,addr=53
	_TM0IN .ds 1
	.ends
	_TM0CNT_SysRegDefine.c .section bank0,addr=54
	_TM0CNT .ds 1
	.ends
	_TM1CON_SysRegDefine.c .section bank0,addr=55
	_TM1CON .ds 1
	.ends
	_TM1IN_SysRegDefine.c .section bank0,addr=56
	_TM1IN .ds 1
	.ends
	_TM1CNT_SysRegDefine.c .section bank0,addr=57
	_TM1CNT .ds 1
	.ends
	_INTF3_SysRegDefine.c .section bank0,addr=90
	_INTF3 .ds 1
	.ends
	_INTE3_SysRegDefine.c .section bank0,addr=91
	_INTE3 .ds 1
	.ends
	_I2CCON_SysRegDefine.c .section bank0,addr=104
	_I2CCON .ds 1
	.ends
	_I2CDAT_SysRegDefine.c .section bank0,addr=105
	_I2CDAT .ds 1
	.ends
	_I2CISR_SysRegDefine.c .section bank0,addr=106
	_I2CISR .ds 1
	.ends
	_ADCON_SysRegDefine.c .section bank0,addr=107
	_ADCON .ds 1
	.ends
	_WDT_TRIM_SysRegDefine.c .section bank0,addr=109
	_WDT_TRIM .ds 1
	.ends
	_ICK_TRIM_SysRegDefine.c .section bank0,addr=110
	_ICK_TRIM .ds 1
	.ends
	_VS_TRIM_SysRegDefine.c .section bank0,addr=111
	_VS_TRIM .ds 1
	.ends
	_METCH_SysRegDefine.c .section bank0,addr=126
	_METCH .ds 1
	.ends
	_I2CADR_SysRegDefine.c .section bank0,addr=127
	_I2CADR .ds 1
	.ends
	_Z_SysRegDefine.c .section bank0,addr=4,bitfield=0,uninit
	_Z .ds 1
	.ends
	_C_SysRegDefine.c .section bank0,addr=4,bitfield=1,uninit
	_C .ds 1
	.ends
	_DC_SysRegDefine.c .section bank0,addr=4,bitfield=2,uninit
	_DC .ds 1
	.ends
	_TO_SysRegDefine.c .section bank0,addr=4,bitfield=3,uninit
	_TO .ds 1
	.ends
	_PD_SysRegDefine.c .section bank0,addr=4,bitfield=4,uninit
	_PD .ds 1
	.ends
	_E0IF_SysRegDefine.c .section bank0,addr=6,bitfield=0,uninit
	_E0IF .ds 1
	.ends
	_E1IF_SysRegDefine.c .section bank0,addr=6,bitfield=1,uninit
	_E1IF .ds 1
	.ends
	_ADIF_SysRegDefine.c .section bank0,addr=6,bitfield=2,uninit
	_ADIF .ds 1
	.ends
	_TM0IF_SysRegDefine.c .section bank0,addr=6,bitfield=4,uninit
	_TM0IF .ds 1
	.ends
	_TM1IF_SysRegDefine.c .section bank0,addr=6,bitfield=5,uninit
	_TM1IF .ds 1
	.ends
	_E0IE_SysRegDefine.c .section bank0,addr=7,bitfield=0,uninit
	_E0IE .ds 1
	.ends
	_E1IE_SysRegDefine.c .section bank0,addr=7,bitfield=1,uninit
	_E1IE .ds 1
	.ends
	_ADIE_SysRegDefine.c .section bank0,addr=7,bitfield=2,uninit
	_ADIE .ds 1
	.ends
	_TM0IE_SysRegDefine.c .section bank0,addr=7,bitfield=4,uninit
	_TM0IE .ds 1
	.ends
	_TM1IE_SysRegDefine.c .section bank0,addr=7,bitfield=5,uninit
	_TM1IE .ds 1
	.ends
	_GIE_SysRegDefine.c .section bank0,addr=7,bitfield=7,uninit
	_GIE .ds 1
	.ends
	_PAGE0_SysRegDefine.c .section bank0,addr=8,bitfield=0,uninit
	_PAGE0 .ds 1
	.ends
	_PAGE1_SysRegDefine.c .section bank0,addr=8,bitfield=1,uninit
	_PAGE1 .ds 1
	.ends
	_IRP1_SysRegDefine.c .section bank0,addr=8,bitfield=6,uninit
	_IRP1 .ds 1
	.ends
	_IRP0_SysRegDefine.c .section bank0,addr=8,bitfield=7,uninit
	_IRP0 .ds 1
	.ends
	_WDT_CLK_EN_SysRegDefine.c .section bank0,addr=9,bitfield=2,uninit
	_WDT_CLK_EN .ds 1
	.ends
	_M3_CK_SysRegDefine.c .section bank0,addr=9,bitfield=6,uninit
	_M3_CK .ds 1
	.ends
	_PARH_0_SysRegDefine.c .section bank0,addr=10,bitfield=0,uninit
	_PARH_0 .ds 1
	.ends
	_PARH_1_SysRegDefine.c .section bank0,addr=10,bitfield=1,uninit
	_PARH_1 .ds 1
	.ends
	_PARH_2_SysRegDefine.c .section bank0,addr=10,bitfield=2,uninit
	_PARH_2 .ds 1
	.ends
	_PARH_3_SysRegDefine.c .section bank0,addr=10,bitfield=3,uninit
	_PARH_3 .ds 1
	.ends
	_PARH_4_SysRegDefine.c .section bank0,addr=10,bitfield=4,uninit
	_PARH_4 .ds 1
	.ends
	_PARH_5_SysRegDefine.c .section bank0,addr=10,bitfield=5,uninit
	_PARH_5 .ds 1
	.ends
	_READ_CHECK_SysRegDefine.c .section bank0,addr=10,bitfield=6,uninit
	_READ_CHECK .ds 1
	.ends
	_PROG_BUSY_SysRegDefine.c .section bank0,addr=10,bitfield=7,uninit
	_PROG_BUSY .ds 1
	.ends
	_PARL_0_SysRegDefine.c .section bank0,addr=11,bitfield=0,uninit
	_PARL_0 .ds 1
	.ends
	_PARL_1_SysRegDefine.c .section bank0,addr=11,bitfield=1,uninit
	_PARL_1 .ds 1
	.ends
	_PARL_2_SysRegDefine.c .section bank0,addr=11,bitfield=2,uninit
	_PARL_2 .ds 1
	.ends
	_PARL_3_SysRegDefine.c .section bank0,addr=11,bitfield=3,uninit
	_PARL_3 .ds 1
	.ends
	_PARL_4_SysRegDefine.c .section bank0,addr=11,bitfield=4,uninit
	_PARL_4 .ds 1
	.ends
	_PARL_5_SysRegDefine.c .section bank0,addr=11,bitfield=5,uninit
	_PARL_5 .ds 1
	.ends
	_PARL_6_SysRegDefine.c .section bank0,addr=11,bitfield=6,uninit
	_PARL_6 .ds 1
	.ends
	_PARL_7_SysRegDefine.c .section bank0,addr=11,bitfield=7,uninit
	_PARL_7 .ds 1
	.ends
	_EDAT_0_SysRegDefine.c .section bank0,addr=12,bitfield=0,uninit
	_EDAT_0 .ds 1
	.ends
	_EDAT_1_SysRegDefine.c .section bank0,addr=12,bitfield=1,uninit
	_EDAT_1 .ds 1
	.ends
	_EDAT_2_SysRegDefine.c .section bank0,addr=12,bitfield=2,uninit
	_EDAT_2 .ds 1
	.ends
	_EDAT_3_SysRegDefine.c .section bank0,addr=12,bitfield=3,uninit
	_EDAT_3 .ds 1
	.ends
	_EDAT_4_SysRegDefine.c .section bank0,addr=12,bitfield=4,uninit
	_EDAT_4 .ds 1
	.ends
	_EDAT_5_SysRegDefine.c .section bank0,addr=12,bitfield=5,uninit
	_EDAT_5 .ds 1
	.ends
	_EDAT_6_SysRegDefine.c .section bank0,addr=12,bitfield=6,uninit
	_EDAT_6 .ds 1
	.ends
	_EDAT_7_SysRegDefine.c .section bank0,addr=12,bitfield=7,uninit
	_EDAT_7 .ds 1
	.ends
	_EOPEN_0_SysRegDefine.c .section bank0,addr=13,bitfield=0,uninit
	_EOPEN_0 .ds 1
	.ends
	_EOPEN_1_SysRegDefine.c .section bank0,addr=13,bitfield=1,uninit
	_EOPEN_1 .ds 1
	.ends
	_EOPEN_2_SysRegDefine.c .section bank0,addr=13,bitfield=2,uninit
	_EOPEN_2 .ds 1
	.ends
	_EOPEN_3_SysRegDefine.c .section bank0,addr=13,bitfield=3,uninit
	_EOPEN_3 .ds 1
	.ends
	_EOPEN_4_SysRegDefine.c .section bank0,addr=13,bitfield=4,uninit
	_EOPEN_4 .ds 1
	.ends
	_EOPEN_5_SysRegDefine.c .section bank0,addr=13,bitfield=5,uninit
	_EOPEN_5 .ds 1
	.ends
	_EOPEN_6_SysRegDefine.c .section bank0,addr=13,bitfield=6,uninit
	_EOPEN_6 .ds 1
	.ends
	_EOPEN_7_SysRegDefine.c .section bank0,addr=13,bitfield=7,uninit
	_EOPEN_7 .ds 1
	.ends
	_WDTS_0_SysRegDefine.c .section bank0,addr=14,bitfield=0,uninit
	_WDTS_0 .ds 1
	.ends
	_WDTS_1_SysRegDefine.c .section bank0,addr=14,bitfield=1,uninit
	_WDTS_1 .ds 1
	.ends
	_WDTS_2_SysRegDefine.c .section bank0,addr=14,bitfield=2,uninit
	_WDTS_2 .ds 1
	.ends
	_I2C_DIV_0_SysRegDefine.c .section bank0,addr=14,bitfield=3,uninit
	_I2C_DIV_0 .ds 1
	.ends
	_I2C_DIV_1_SysRegDefine.c .section bank0,addr=14,bitfield=4,uninit
	_I2C_DIV_1 .ds 1
	.ends
	_ROOT_EN_SysRegDefine.c .section bank0,addr=14,bitfield=6,uninit
	_ROOT_EN .ds 1
	.ends
	_WDTEN_SysRegDefine.c .section bank0,addr=14,bitfield=7,uninit
	_WDTEN .ds 1
	.ends
	_WDTIN_0_SysRegDefine.c .section bank0,addr=15,bitfield=0,uninit
	_WDTIN_0 .ds 1
	.ends
	_WDTIN_1_SysRegDefine.c .section bank0,addr=15,bitfield=1,uninit
	_WDTIN_1 .ds 1
	.ends
	_WDTIN_2_SysRegDefine.c .section bank0,addr=15,bitfield=2,uninit
	_WDTIN_2 .ds 1
	.ends
	_WDTIN_3_SysRegDefine.c .section bank0,addr=15,bitfield=3,uninit
	_WDTIN_3 .ds 1
	.ends
	_WDTIN_4_SysRegDefine.c .section bank0,addr=15,bitfield=4,uninit
	_WDTIN_4 .ds 1
	.ends
	_WDTIN_5_SysRegDefine.c .section bank0,addr=15,bitfield=5,uninit
	_WDTIN_5 .ds 1
	.ends
	_WDTIN_6_SysRegDefine.c .section bank0,addr=15,bitfield=6,uninit
	_WDTIN_6 .ds 1
	.ends
	_WDTIN_7_SysRegDefine.c .section bank0,addr=15,bitfield=7,uninit
	_WDTIN_7 .ds 1
	.ends
	_ADO_8_SysRegDefine.c .section bank0,addr=17,bitfield=0,uninit
	_ADO_8 .ds 1
	.ends
	_ADO_9_SysRegDefine.c .section bank0,addr=17,bitfield=1,uninit
	_ADO_9 .ds 1
	.ends
	_ADO_10_SysRegDefine.c .section bank0,addr=17,bitfield=2,uninit
	_ADO_10 .ds 1
	.ends
	_ADO_11_SysRegDefine.c .section bank0,addr=17,bitfield=3,uninit
	_ADO_11 .ds 1
	.ends
	_ADO_12_SysRegDefine.c .section bank0,addr=17,bitfield=4,uninit
	_ADO_12 .ds 1
	.ends
	_ADO_13_SysRegDefine.c .section bank0,addr=17,bitfield=5,uninit
	_ADO_13 .ds 1
	.ends
	_ADO_14_SysRegDefine.c .section bank0,addr=17,bitfield=6,uninit
	_ADO_14 .ds 1
	.ends
	_ADO_15_SysRegDefine.c .section bank0,addr=17,bitfield=7,uninit
	_ADO_15 .ds 1
	.ends
	_ROOT_0_SysRegDefine.c .section bank0,addr=19,bitfield=0,uninit
	_ROOT_0 .ds 1
	.ends
	_ROOT_1_SysRegDefine.c .section bank0,addr=19,bitfield=1,uninit
	_ROOT_1 .ds 1
	.ends
	_ROOT_2_SysRegDefine.c .section bank0,addr=19,bitfield=2,uninit
	_ROOT_2 .ds 1
	.ends
	_ROOT_3_SysRegDefine.c .section bank0,addr=19,bitfield=3,uninit
	_ROOT_3 .ds 1
	.ends
	_ROOT_4_SysRegDefine.c .section bank0,addr=19,bitfield=4,uninit
	_ROOT_4 .ds 1
	.ends
	_ROOT_5_SysRegDefine.c .section bank0,addr=19,bitfield=5,uninit
	_ROOT_5 .ds 1
	.ends
	_ROOT_6_SysRegDefine.c .section bank0,addr=19,bitfield=6,uninit
	_ROOT_6 .ds 1
	.ends
	_ROOT_7_SysRegDefine.c .section bank0,addr=19,bitfield=7,uninit
	_ROOT_7 .ds 1
	.ends
	_ILOPF_SysRegDefine.c .section bank0,addr=20,bitfield=1,uninit
	_ILOPF .ds 1
	.ends
	_EMCF_SysRegDefine.c .section bank0,addr=20,bitfield=2,uninit
	_EMCF .ds 1
	.ends
	_LVDF_SysRegDefine.c .section bank0,addr=20,bitfield=3,uninit
	_LVDF .ds 1
	.ends
	_CHOPM_0_SysRegDefine.c .section bank0,addr=22,bitfield=0,uninit
	_CHOPM_0 .ds 1
	.ends
	_CHOPM_1_SysRegDefine.c .section bank0,addr=22,bitfield=1,uninit
	_CHOPM_1 .ds 1
	.ends
	_S_GAIN_0_SysRegDefine.c .section bank0,addr=22,bitfield=3,uninit
	_S_GAIN_0 .ds 1
	.ends
	_S_GAIN_1_SysRegDefine.c .section bank0,addr=22,bitfield=4,uninit
	_S_GAIN_1 .ds 1
	.ends
	_ADSC_SysRegDefine.c .section bank0,addr=22,bitfield=7,uninit
	_ADSC .ds 1
	.ends
	_ADEN_SysRegDefine.c .section bank0,addr=23,bitfield=0,uninit
	_ADEN .ds 1
	.ends
	_SINL_0_SysRegDefine.c .section bank0,addr=23,bitfield=1,uninit
	_SINL_0 .ds 1
	.ends
	_SINL_1_SysRegDefine.c .section bank0,addr=23,bitfield=2,uninit
	_SINL_1 .ds 1
	.ends
	_BGID_SysRegDefine.c .section bank0,addr=23,bitfield=3,uninit
	_BGID .ds 1
	.ends
	_BGR_ENB_SysRegDefine.c .section bank0,addr=23,bitfield=4,uninit
	_BGR_ENB .ds 1
	.ends
	_LDOS_0_SysRegDefine.c .section bank0,addr=23,bitfield=5,uninit
	_LDOS_0 .ds 1
	.ends
	_LDOS_1_SysRegDefine.c .section bank0,addr=23,bitfield=6,uninit
	_LDOS_1 .ds 1
	.ends
	_LDOEN_SysRegDefine.c .section bank0,addr=23,bitfield=7,uninit
	_LDOEN .ds 1
	.ends
	_LB_RST_CON_SysRegDefine.c .section bank0,addr=27,bitfield=0,uninit
	_LB_RST_CON .ds 1
	.ends
	_LBOUT_SysRegDefine.c .section bank0,addr=27,bitfield=1,uninit
	_LBOUT .ds 1
	.ends
	_SILB_0_SysRegDefine.c .section bank0,addr=27,bitfield=2,uninit
	_SILB_0 .ds 1
	.ends
	_SILB_1_SysRegDefine.c .section bank0,addr=27,bitfield=3,uninit
	_SILB_1 .ds 1
	.ends
	_SILB_2_SysRegDefine.c .section bank0,addr=27,bitfield=4,uninit
	_SILB_2 .ds 1
	.ends
	_AIENB1_SysRegDefine.c .section bank0,addr=27,bitfield=5,uninit
	_AIENB1 .ds 1
	.ends
	_LVDEN_SysRegDefine.c .section bank0,addr=27,bitfield=7,uninit
	_LVDEN .ds 1
	.ends
	_ADO_0_SysRegDefine.c .section bank0,addr=28,bitfield=0,uninit
	_ADO_0 .ds 1
	.ends
	_ADO_1_SysRegDefine.c .section bank0,addr=28,bitfield=1,uninit
	_ADO_1 .ds 1
	.ends
	_ADO_2_SysRegDefine.c .section bank0,addr=28,bitfield=2,uninit
	_ADO_2 .ds 1
	.ends
	_ADO_3_SysRegDefine.c .section bank0,addr=28,bitfield=3,uninit
	_ADO_3 .ds 1
	.ends
	_ADO_4_SysRegDefine.c .section bank0,addr=28,bitfield=4,uninit
	_ADO_4 .ds 1
	.ends
	_ADO_5_SysRegDefine.c .section bank0,addr=28,bitfield=5,uninit
	_ADO_5 .ds 1
	.ends
	_ADO_6_SysRegDefine.c .section bank0,addr=28,bitfield=6,uninit
	_ADO_6 .ds 1
	.ends
	_ADO_7_SysRegDefine.c .section bank0,addr=28,bitfield=7,uninit
	_ADO_7 .ds 1
	.ends
	_PT1_0_SysRegDefine.c .section bank0,addr=29,bitfield=0,uninit
	_PT1_0 .ds 1
	.ends
	_PT1_1_SysRegDefine.c .section bank0,addr=29,bitfield=1,uninit
	_PT1_1 .ds 1
	.ends
	_PT1_2_SysRegDefine.c .section bank0,addr=29,bitfield=2,uninit
	_PT1_2 .ds 1
	.ends
	_PT1_3_SysRegDefine.c .section bank0,addr=29,bitfield=3,uninit
	_PT1_3 .ds 1
	.ends
	_PT1_4_SysRegDefine.c .section bank0,addr=29,bitfield=4,uninit
	_PT1_4 .ds 1
	.ends
	_PT1_5_SysRegDefine.c .section bank0,addr=29,bitfield=5,uninit
	_PT1_5 .ds 1
	.ends
	_PT1EN_0_SysRegDefine.c .section bank0,addr=30,bitfield=0,uninit
	_PT1EN_0 .ds 1
	.ends
	_PT1EN_1_SysRegDefine.c .section bank0,addr=30,bitfield=1,uninit
	_PT1EN_1 .ds 1
	.ends
	_PT1EN_2_SysRegDefine.c .section bank0,addr=30,bitfield=2,uninit
	_PT1EN_2 .ds 1
	.ends
	_PT1EN_3_SysRegDefine.c .section bank0,addr=30,bitfield=3,uninit
	_PT1EN_3 .ds 1
	.ends
	_PT1EN_4_SysRegDefine.c .section bank0,addr=30,bitfield=4,uninit
	_PT1EN_4 .ds 1
	.ends
	_PT1EN_5_SysRegDefine.c .section bank0,addr=30,bitfield=5,uninit
	_PT1EN_5 .ds 1
	.ends
	_PT1UP_0_SysRegDefine.c .section bank0,addr=31,bitfield=0,uninit
	_PT1UP_0 .ds 1
	.ends
	_PT1UP_1_SysRegDefine.c .section bank0,addr=31,bitfield=1,uninit
	_PT1UP_1 .ds 1
	.ends
	_PT10_OD_SysRegDefine.c .section bank0,addr=44,bitfield=0,uninit
	_PT10_OD .ds 1
	.ends
	_PT11_OD_SysRegDefine.c .section bank0,addr=44,bitfield=1,uninit
	_PT11_OD .ds 1
	.ends
	_I2C_FLT_SysRegDefine.c .section bank0,addr=44,bitfield=2,uninit
	_I2C_FLT .ds 1
	.ends
	_PT10_VDD_SysRegDefine.c .section bank0,addr=44,bitfield=3,uninit
	_PT10_VDD .ds 1
	.ends
	_PT11_VDD_SysRegDefine.c .section bank0,addr=44,bitfield=4,uninit
	_PT11_VDD .ds 1
	.ends
	_I2C_VDD_SysRegDefine.c .section bank0,addr=44,bitfield=5,uninit
	_I2C_VDD .ds 1
	.ends
	_PT14_VDD_SysRegDefine.c .section bank0,addr=44,bitfield=6,uninit
	_PT14_VDD .ds 1
	.ends
	_PT15_VDD_SysRegDefine.c .section bank0,addr=44,bitfield=7,uninit
	_PT15_VDD .ds 1
	.ends
	_E0M_0_SysRegDefine.c .section bank0,addr=45,bitfield=0,uninit
	_E0M_0 .ds 1
	.ends
	_E0M_1_SysRegDefine.c .section bank0,addr=45,bitfield=1,uninit
	_E0M_1 .ds 1
	.ends
	_E1M_0_SysRegDefine.c .section bank0,addr=45,bitfield=2,uninit
	_E1M_0 .ds 1
	.ends
	_E1M_1_SysRegDefine.c .section bank0,addr=45,bitfield=3,uninit
	_E1M_1 .ds 1
	.ends
	_PTW0_0_SysRegDefine.c .section bank0,addr=46,bitfield=0,uninit
	_PTW0_0 .ds 1
	.ends
	_PTW0_1_SysRegDefine.c .section bank0,addr=46,bitfield=1,uninit
	_PTW0_1 .ds 1
	.ends
	_PTW0_2_SysRegDefine.c .section bank0,addr=46,bitfield=2,uninit
	_PTW0_2 .ds 1
	.ends
	_PTW1_0_SysRegDefine.c .section bank0,addr=47,bitfield=0,uninit
	_PTW1_0 .ds 1
	.ends
	_PTW1_1_SysRegDefine.c .section bank0,addr=47,bitfield=1,uninit
	_PTW1_1 .ds 1
	.ends
	_PTW1_2_SysRegDefine.c .section bank0,addr=47,bitfield=2,uninit
	_PTW1_2 .ds 1
	.ends
	_T0SEL_SysRegDefine.c .section bank0,addr=52,bitfield=0,uninit
	_T0SEL .ds 1
	.ends
	_T0RSTB_SysRegDefine.c .section bank0,addr=52,bitfield=2,uninit
	_T0RSTB .ds 1
	.ends
	_T0RATE_0_SysRegDefine.c .section bank0,addr=52,bitfield=4,uninit
	_T0RATE_0 .ds 1
	.ends
	_T0RATE_1_SysRegDefine.c .section bank0,addr=52,bitfield=5,uninit
	_T0RATE_1 .ds 1
	.ends
	_T0RATE_2_SysRegDefine.c .section bank0,addr=52,bitfield=6,uninit
	_T0RATE_2 .ds 1
	.ends
	_T0EN_SysRegDefine.c .section bank0,addr=52,bitfield=7,uninit
	_T0EN .ds 1
	.ends
	_TM0IN_0_SysRegDefine.c .section bank0,addr=53,bitfield=0,uninit
	_TM0IN_0 .ds 1
	.ends
	_TM0IN_1_SysRegDefine.c .section bank0,addr=53,bitfield=1,uninit
	_TM0IN_1 .ds 1
	.ends
	_TM0IN_2_SysRegDefine.c .section bank0,addr=53,bitfield=2,uninit
	_TM0IN_2 .ds 1
	.ends
	_TM0IN_3_SysRegDefine.c .section bank0,addr=53,bitfield=3,uninit
	_TM0IN_3 .ds 1
	.ends
	_TM0IN_4_SysRegDefine.c .section bank0,addr=53,bitfield=4,uninit
	_TM0IN_4 .ds 1
	.ends
	_TM0IN_5_SysRegDefine.c .section bank0,addr=53,bitfield=5,uninit
	_TM0IN_5 .ds 1
	.ends
	_TM0IN_6_SysRegDefine.c .section bank0,addr=53,bitfield=6,uninit
	_TM0IN_6 .ds 1
	.ends
	_TM0IN_7_SysRegDefine.c .section bank0,addr=53,bitfield=7,uninit
	_TM0IN_7 .ds 1
	.ends
	_TM0CNT_0_SysRegDefine.c .section bank0,addr=54,bitfield=0,uninit
	_TM0CNT_0 .ds 1
	.ends
	_TM0CNT_1_SysRegDefine.c .section bank0,addr=54,bitfield=1,uninit
	_TM0CNT_1 .ds 1
	.ends
	_TM0CNT_2_SysRegDefine.c .section bank0,addr=54,bitfield=2,uninit
	_TM0CNT_2 .ds 1
	.ends
	_TM0CNT_3_SysRegDefine.c .section bank0,addr=54,bitfield=3,uninit
	_TM0CNT_3 .ds 1
	.ends
	_TM0CNT_4_SysRegDefine.c .section bank0,addr=54,bitfield=4,uninit
	_TM0CNT_4 .ds 1
	.ends
	_TM0CNT_5_SysRegDefine.c .section bank0,addr=54,bitfield=5,uninit
	_TM0CNT_5 .ds 1
	.ends
	_TM0CNT_6_SysRegDefine.c .section bank0,addr=54,bitfield=6,uninit
	_TM0CNT_6 .ds 1
	.ends
	_TM0CNT_7_SysRegDefine.c .section bank0,addr=54,bitfield=7,uninit
	_TM0CNT_7 .ds 1
	.ends
	_T1SEL_SysRegDefine.c .section bank0,addr=55,bitfield=0,uninit
	_T1SEL .ds 1
	.ends
	_T1RSTB_SysRegDefine.c .section bank0,addr=55,bitfield=2,uninit
	_T1RSTB .ds 1
	.ends
	_T1RATE_0_SysRegDefine.c .section bank0,addr=55,bitfield=4,uninit
	_T1RATE_0 .ds 1
	.ends
	_T1RATE_1_SysRegDefine.c .section bank0,addr=55,bitfield=5,uninit
	_T1RATE_1 .ds 1
	.ends
	_T1RATE_2_SysRegDefine.c .section bank0,addr=55,bitfield=6,uninit
	_T1RATE_2 .ds 1
	.ends
	_T1EN_SysRegDefine.c .section bank0,addr=55,bitfield=7,uninit
	_T1EN .ds 1
	.ends
	_TM1IN_0_SysRegDefine.c .section bank0,addr=56,bitfield=0,uninit
	_TM1IN_0 .ds 1
	.ends
	_TM1IN_1_SysRegDefine.c .section bank0,addr=56,bitfield=1,uninit
	_TM1IN_1 .ds 1
	.ends
	_TM1IN_2_SysRegDefine.c .section bank0,addr=56,bitfield=2,uninit
	_TM1IN_2 .ds 1
	.ends
	_TM1IN_3_SysRegDefine.c .section bank0,addr=56,bitfield=3,uninit
	_TM1IN_3 .ds 1
	.ends
	_TM1IN_4_SysRegDefine.c .section bank0,addr=56,bitfield=4,uninit
	_TM1IN_4 .ds 1
	.ends
	_TM1IN_5_SysRegDefine.c .section bank0,addr=56,bitfield=5,uninit
	_TM1IN_5 .ds 1
	.ends
	_TM1IN_6_SysRegDefine.c .section bank0,addr=56,bitfield=6,uninit
	_TM1IN_6 .ds 1
	.ends
	_TM1IN_7_SysRegDefine.c .section bank0,addr=56,bitfield=7,uninit
	_TM1IN_7 .ds 1
	.ends
	_TM1CNT_0_SysRegDefine.c .section bank0,addr=57,bitfield=0,uninit
	_TM1CNT_0 .ds 1
	.ends
	_TM1CNT_1_SysRegDefine.c .section bank0,addr=57,bitfield=1,uninit
	_TM1CNT_1 .ds 1
	.ends
	_TM1CNT_2_SysRegDefine.c .section bank0,addr=57,bitfield=2,uninit
	_TM1CNT_2 .ds 1
	.ends
	_TM1CNT_3_SysRegDefine.c .section bank0,addr=57,bitfield=3,uninit
	_TM1CNT_3 .ds 1
	.ends
	_TM1CNT_4_SysRegDefine.c .section bank0,addr=57,bitfield=4,uninit
	_TM1CNT_4 .ds 1
	.ends
	_TM1CNT_5_SysRegDefine.c .section bank0,addr=57,bitfield=5,uninit
	_TM1CNT_5 .ds 1
	.ends
	_TM1CNT_6_SysRegDefine.c .section bank0,addr=57,bitfield=6,uninit
	_TM1CNT_6 .ds 1
	.ends
	_TM1CNT_7_SysRegDefine.c .section bank0,addr=57,bitfield=7,uninit
	_TM1CNT_7 .ds 1
	.ends
	_I2C_STIF_SysRegDefine.c .section bank0,addr=90,bitfield=2,uninit
	_I2C_STIF .ds 1
	.ends
	_I2C_RIF_SysRegDefine.c .section bank0,addr=90,bitfield=6,uninit
	_I2C_RIF .ds 1
	.ends
	_I2C_TIF_SysRegDefine.c .section bank0,addr=90,bitfield=7,uninit
	_I2C_TIF .ds 1
	.ends
	_I2C_STIE_SysRegDefine.c .section bank0,addr=91,bitfield=2,uninit
	_I2C_STIE .ds 1
	.ends
	_I2C_RIE_SysRegDefine.c .section bank0,addr=91,bitfield=6,uninit
	_I2C_RIE .ds 1
	.ends
	_I2C_TIE_SysRegDefine.c .section bank0,addr=91,bitfield=7,uninit
	_I2C_TIE .ds 1
	.ends
	_I2CSTUS_0_SysRegDefine.c .section bank0,addr=104,bitfield=0,uninit
	_I2CSTUS_0 .ds 1
	.ends
	_I2CSTUS_1_SysRegDefine.c .section bank0,addr=104,bitfield=1,uninit
	_I2CSTUS_1 .ds 1
	.ends
	_I2CSTUS_2_SysRegDefine.c .section bank0,addr=104,bitfield=2,uninit
	_I2CSTUS_2 .ds 1
	.ends
	_I2CSTUS_3_SysRegDefine.c .section bank0,addr=104,bitfield=3,uninit
	_I2CSTUS_3 .ds 1
	.ends
	_ACK_EN_SysRegDefine.c .section bank0,addr=104,bitfield=4,uninit
	_ACK_EN .ds 1
	.ends
	_CST_EN_SysRegDefine.c .section bank0,addr=104,bitfield=5,uninit
	_CST_EN .ds 1
	.ends
	_AWK_EN_SysRegDefine.c .section bank0,addr=104,bitfield=6,uninit
	_AWK_EN .ds 1
	.ends
	_I2C_EN_SysRegDefine.c .section bank0,addr=104,bitfield=7,uninit
	_I2C_EN .ds 1
	.ends
	_I2CDAT_0_SysRegDefine.c .section bank0,addr=105,bitfield=0,uninit
	_I2CDAT_0 .ds 1
	.ends
	_I2CDAT_1_SysRegDefine.c .section bank0,addr=105,bitfield=1,uninit
	_I2CDAT_1 .ds 1
	.ends
	_I2CDAT_2_SysRegDefine.c .section bank0,addr=105,bitfield=2,uninit
	_I2CDAT_2 .ds 1
	.ends
	_I2CDAT_3_SysRegDefine.c .section bank0,addr=105,bitfield=3,uninit
	_I2CDAT_3 .ds 1
	.ends
	_I2CDAT_4_SysRegDefine.c .section bank0,addr=105,bitfield=4,uninit
	_I2CDAT_4 .ds 1
	.ends
	_I2CDAT_5_SysRegDefine.c .section bank0,addr=105,bitfield=5,uninit
	_I2CDAT_5 .ds 1
	.ends
	_I2CDAT_6_SysRegDefine.c .section bank0,addr=105,bitfield=6,uninit
	_I2CDAT_6 .ds 1
	.ends
	_I2CDAT_7_SysRegDefine.c .section bank0,addr=105,bitfield=7,uninit
	_I2CDAT_7 .ds 1
	.ends
	_TXE_SysRegDefine.c .section bank0,addr=106,bitfield=0,uninit
	_TXE .ds 1
	.ends
	_ADM_0_SysRegDefine.c .section bank0,addr=107,bitfield=0,uninit
	_ADM_0 .ds 1
	.ends
	_ADM_1_SysRegDefine.c .section bank0,addr=107,bitfield=1,uninit
	_ADM_1 .ds 1
	.ends
	_AINOUT_0_SysRegDefine.c .section bank0,addr=107,bitfield=4,uninit
	_AINOUT_0 .ds 1
	.ends
	_AINOUT_1_SysRegDefine.c .section bank0,addr=107,bitfield=5,uninit
	_AINOUT_1 .ds 1
	.ends
	_VS_LIMIT_SysRegDefine.c .section bank0,addr=107,bitfield=6,uninit
	_VS_LIMIT .ds 1
	.ends
	_VS0_OEN_SysRegDefine.c .section bank0,addr=107,bitfield=7,uninit
	_VS0_OEN .ds 1
	.ends
	_WDT_TRIM_0_SysRegDefine.c .section bank0,addr=109,bitfield=0,uninit
	_WDT_TRIM_0 .ds 1
	.ends
	_WDT_TRIM_1_SysRegDefine.c .section bank0,addr=109,bitfield=1,uninit
	_WDT_TRIM_1 .ds 1
	.ends
	_WDT_TRIM_2_SysRegDefine.c .section bank0,addr=109,bitfield=2,uninit
	_WDT_TRIM_2 .ds 1
	.ends
	_WDT_TRIM_3_SysRegDefine.c .section bank0,addr=109,bitfield=3,uninit
	_WDT_TRIM_3 .ds 1
	.ends
	_TMOD_0_SysRegDefine.c .section bank0,addr=109,bitfield=6,uninit
	_TMOD_0 .ds 1
	.ends
	_TMOD_1_SysRegDefine.c .section bank0,addr=109,bitfield=7,uninit
	_TMOD_1 .ds 1
	.ends
	_ICK_TRIM_0_SysRegDefine.c .section bank0,addr=110,bitfield=0,uninit
	_ICK_TRIM_0 .ds 1
	.ends
	_ICK_TRIM_1_SysRegDefine.c .section bank0,addr=110,bitfield=1,uninit
	_ICK_TRIM_1 .ds 1
	.ends
	_ICK_TRIM_2_SysRegDefine.c .section bank0,addr=110,bitfield=2,uninit
	_ICK_TRIM_2 .ds 1
	.ends
	_ICK_TRIM_3_SysRegDefine.c .section bank0,addr=110,bitfield=3,uninit
	_ICK_TRIM_3 .ds 1
	.ends
	_ICK_TRIM_4_SysRegDefine.c .section bank0,addr=110,bitfield=4,uninit
	_ICK_TRIM_4 .ds 1
	.ends
	_ICK_TRIM_5_SysRegDefine.c .section bank0,addr=110,bitfield=5,uninit
	_ICK_TRIM_5 .ds 1
	.ends
	_ICK_TRIM_6_SysRegDefine.c .section bank0,addr=110,bitfield=6,uninit
	_ICK_TRIM_6 .ds 1
	.ends
	_ICK_TRIM_7_SysRegDefine.c .section bank0,addr=110,bitfield=7,uninit
	_ICK_TRIM_7 .ds 1
	.ends
	_VS_TRIM_0_SysRegDefine.c .section bank0,addr=111,bitfield=0,uninit
	_VS_TRIM_0 .ds 1
	.ends
	_VS_TRIM_1_SysRegDefine.c .section bank0,addr=111,bitfield=1,uninit
	_VS_TRIM_1 .ds 1
	.ends
	_VS_TRIM_2_SysRegDefine.c .section bank0,addr=111,bitfield=2,uninit
	_VS_TRIM_2 .ds 1
	.ends
	_VS_TRIM_3_SysRegDefine.c .section bank0,addr=111,bitfield=3,uninit
	_VS_TRIM_3 .ds 1
	.ends
	_LVD_TRIM_0_SysRegDefine.c .section bank0,addr=111,bitfield=4,uninit
	_LVD_TRIM_0 .ds 1
	.ends
	_LVD_TRIM_1_SysRegDefine.c .section bank0,addr=111,bitfield=5,uninit
	_LVD_TRIM_1 .ds 1
	.ends
	_LVD_TRIM_2_SysRegDefine.c .section bank0,addr=111,bitfield=6,uninit
	_LVD_TRIM_2 .ds 1
	.ends
	_SIM_RST_SysRegDefine.c .section bank0,addr=111,bitfield=7,uninit
	_SIM_RST .ds 1
	.ends
	_EVPP_EN_SysRegDefine.c .section bank0,addr=126,bitfield=3,uninit
	_EVPP_EN .ds 1
	.ends
	_METCH_0_SysRegDefine.c .section bank0,addr=126,bitfield=4,uninit
	_METCH_0 .ds 1
	.ends
	_METCH_1_SysRegDefine.c .section bank0,addr=126,bitfield=5,uninit
	_METCH_1 .ds 1
	.ends
	_METCH_2_SysRegDefine.c .section bank0,addr=126,bitfield=6,uninit
	_METCH_2 .ds 1
	.ends
	_METCH_3_SysRegDefine.c .section bank0,addr=126,bitfield=7,uninit
	_METCH_3 .ds 1
	.ends
	_GC_EN_SysRegDefine.c .section bank0,addr=127,bitfield=0,uninit
	_GC_EN .ds 1
	.ends
	_I2CADR_0_SysRegDefine.c .section bank0,addr=127,bitfield=1,uninit
	_I2CADR_0 .ds 1
	.ends
	_I2CADR_1_SysRegDefine.c .section bank0,addr=127,bitfield=2,uninit
	_I2CADR_1 .ds 1
	.ends
	_I2CADR_2_SysRegDefine.c .section bank0,addr=127,bitfield=3,uninit
	_I2CADR_2 .ds 1
	.ends
	_I2CADR_3_SysRegDefine.c .section bank0,addr=127,bitfield=4,uninit
	_I2CADR_3 .ds 1
	.ends
	_I2CADR_4_SysRegDefine.c .section bank0,addr=127,bitfield=5,uninit
	_I2CADR_4 .ds 1
	.ends
	_I2CADR_5_SysRegDefine.c .section bank0,addr=127,bitfield=6,uninit
	_I2CADR_5 .ds 1
	.ends
	_I2CADR_6_SysRegDefine.c .section bank0,addr=127,bitfield=7,uninit
	_I2CADR_6 .ds 1
	.ends
	.global	_IND0
	.global	_IND1
	.global	_FSR0
	.global	_FSR1
	.global	_STATUS
	.global	_WORK
	.global	_INTF
	.global	_INTE
	.global	_BSR
	.global	_MCK
	.global	_EADRH
	.global	_EADRL
	.global	_EDAT
	.global	_EOPEN
	.global	_WDTCON
	.global	_WDTIN
	.global	_ADOH
	.global	_ROOT
	.global	_RSTSR
	.global	_ADCFG
	.global	_ANACFG
	.global	_LVDCON
	.global	_ADOL
	.global	_PT1
	.global	_PT1EN
	.global	_PT1PU
	.global	_INPUT
	.global	_PTCON
	.global	_PTINT0
	.global	_PTINT1
	.global	_TM0CON
	.global	_TM0IN
	.global	_TM0CNT
	.global	_TM1CON
	.global	_TM1IN
	.global	_TM1CNT
	.global	_INTF3
	.global	_INTE3
	.global	_I2CCON
	.global	_I2CDAT
	.global	_I2CISR
	.global	_ADCON
	.global	_WDT_TRIM
	.global	_ICK_TRIM
	.global	_VS_TRIM
	.global	_METCH
	.global	_I2CADR
	.global	_Z
	.global	_C
	.global	_DC
	.global	_TO
	.global	_PD
	.global	_E0IF
	.global	_E1IF
	.global	_ADIF
	.global	_TM0IF
	.global	_TM1IF
	.global	_E0IE
	.global	_E1IE
	.global	_ADIE
	.global	_TM0IE
	.global	_TM1IE
	.global	_GIE
	.global	_PAGE0
	.global	_PAGE1
	.global	_IRP1
	.global	_IRP0
	.global	_WDT_CLK_EN
	.global	_M3_CK
	.global	_PARH_0
	.global	_PARH_1
	.global	_PARH_2
	.global	_PARH_3
	.global	_PARH_4
	.global	_PARH_5
	.global	_READ_CHECK
	.global	_PROG_BUSY
	.global	_PARL_0
	.global	_PARL_1
	.global	_PARL_2
	.global	_PARL_3
	.global	_PARL_4
	.global	_PARL_5
	.global	_PARL_6
	.global	_PARL_7
	.global	_EDAT_0
	.global	_EDAT_1
	.global	_EDAT_2
	.global	_EDAT_3
	.global	_EDAT_4
	.global	_EDAT_5
	.global	_EDAT_6
	.global	_EDAT_7
	.global	_EOPEN_0
	.global	_EOPEN_1
	.global	_EOPEN_2
	.global	_EOPEN_3
	.global	_EOPEN_4
	.global	_EOPEN_5
	.global	_EOPEN_6
	.global	_EOPEN_7
	.global	_WDTS_0
	.global	_WDTS_1
	.global	_WDTS_2
	.global	_I2C_DIV_0
	.global	_I2C_DIV_1
	.global	_ROOT_EN
	.global	_WDTEN
	.global	_WDTIN_0
	.global	_WDTIN_1
	.global	_WDTIN_2
	.global	_WDTIN_3
	.global	_WDTIN_4
	.global	_WDTIN_5
	.global	_WDTIN_6
	.global	_WDTIN_7
	.global	_ADO_8
	.global	_ADO_9
	.global	_ADO_10
	.global	_ADO_11
	.global	_ADO_12
	.global	_ADO_13
	.global	_ADO_14
	.global	_ADO_15
	.global	_ROOT_0
	.global	_ROOT_1
	.global	_ROOT_2
	.global	_ROOT_3
	.global	_ROOT_4
	.global	_ROOT_5
	.global	_ROOT_6
	.global	_ROOT_7
	.global	_ILOPF
	.global	_EMCF
	.global	_LVDF
	.global	_CHOPM_0
	.global	_CHOPM_1
	.global	_S_GAIN_0
	.global	_S_GAIN_1
	.global	_ADSC
	.global	_ADEN
	.global	_SINL_0
	.global	_SINL_1
	.global	_BGID
	.global	_BGR_ENB
	.global	_LDOS_0
	.global	_LDOS_1
	.global	_LDOEN
	.global	_LB_RST_CON
	.global	_LBOUT
	.global	_SILB_0
	.global	_SILB_1
	.global	_SILB_2
	.global	_AIENB1
	.global	_LVDEN
	.global	_ADO_0
	.global	_ADO_1
	.global	_ADO_2
	.global	_ADO_3
	.global	_ADO_4
	.global	_ADO_5
	.global	_ADO_6
	.global	_ADO_7
	.global	_PT1_0
	.global	_PT1_1
	.global	_PT1_2
	.global	_PT1_3
	.global	_PT1_4
	.global	_PT1_5
	.global	_PT1EN_0
	.global	_PT1EN_1
	.global	_PT1EN_2
	.global	_PT1EN_3
	.global	_PT1EN_4
	.global	_PT1EN_5
	.global	_PT1UP_0
	.global	_PT1UP_1
	.global	_PT10_OD
	.global	_PT11_OD
	.global	_I2C_FLT
	.global	_PT10_VDD
	.global	_PT11_VDD
	.global	_I2C_VDD
	.global	_PT14_VDD
	.global	_PT15_VDD
	.global	_E0M_0
	.global	_E0M_1
	.global	_E1M_0
	.global	_E1M_1
	.global	_PTW0_0
	.global	_PTW0_1
	.global	_PTW0_2
	.global	_PTW1_0
	.global	_PTW1_1
	.global	_PTW1_2
	.global	_T0SEL
	.global	_T0RSTB
	.global	_T0RATE_0
	.global	_T0RATE_1
	.global	_T0RATE_2
	.global	_T0EN
	.global	_TM0IN_0
	.global	_TM0IN_1
	.global	_TM0IN_2
	.global	_TM0IN_3
	.global	_TM0IN_4
	.global	_TM0IN_5
	.global	_TM0IN_6
	.global	_TM0IN_7
	.global	_TM0CNT_0
	.global	_TM0CNT_1
	.global	_TM0CNT_2
	.global	_TM0CNT_3
	.global	_TM0CNT_4
	.global	_TM0CNT_5
	.global	_TM0CNT_6
	.global	_TM0CNT_7
	.global	_T1SEL
	.global	_T1RSTB
	.global	_T1RATE_0
	.global	_T1RATE_1
	.global	_T1RATE_2
	.global	_T1EN
	.global	_TM1IN_0
	.global	_TM1IN_1
	.global	_TM1IN_2
	.global	_TM1IN_3
	.global	_TM1IN_4
	.global	_TM1IN_5
	.global	_TM1IN_6
	.global	_TM1IN_7
	.global	_TM1CNT_0
	.global	_TM1CNT_1
	.global	_TM1CNT_2
	.global	_TM1CNT_3
	.global	_TM1CNT_4
	.global	_TM1CNT_5
	.global	_TM1CNT_6
	.global	_TM1CNT_7
	.global	_I2C_STIF
	.global	_I2C_RIF
	.global	_I2C_TIF
	.global	_I2C_STIE
	.global	_I2C_RIE
	.global	_I2C_TIE
	.global	_I2CSTUS_0
	.global	_I2CSTUS_1
	.global	_I2CSTUS_2
	.global	_I2CSTUS_3
	.global	_ACK_EN
	.global	_CST_EN
	.global	_AWK_EN
	.global	_I2C_EN
	.global	_I2CDAT_0
	.global	_I2CDAT_1
	.global	_I2CDAT_2
	.global	_I2CDAT_3
	.global	_I2CDAT_4
	.global	_I2CDAT_5
	.global	_I2CDAT_6
	.global	_I2CDAT_7
	.global	_TXE
	.global	_ADM_0
	.global	_ADM_1
	.global	_AINOUT_0
	.global	_AINOUT_1
	.global	_VS_LIMIT
	.global	_VS0_OEN
	.global	_WDT_TRIM_0
	.global	_WDT_TRIM_1
	.global	_WDT_TRIM_2
	.global	_WDT_TRIM_3
	.global	_TMOD_0
	.global	_TMOD_1
	.global	_ICK_TRIM_0
	.global	_ICK_TRIM_1
	.global	_ICK_TRIM_2
	.global	_ICK_TRIM_3
	.global	_ICK_TRIM_4
	.global	_ICK_TRIM_5
	.global	_ICK_TRIM_6
	.global	_ICK_TRIM_7
	.global	_VS_TRIM_0
	.global	_VS_TRIM_1
	.global	_VS_TRIM_2
	.global	_VS_TRIM_3
	.global	_LVD_TRIM_0
	.global	_LVD_TRIM_1
	.global	_LVD_TRIM_2
	.global	_SIM_RST
	.global	_EVPP_EN
	.global	_METCH_0
	.global	_METCH_1
	.global	_METCH_2
	.global	_METCH_3
	.global	_GC_EN
	.global	_I2CADR_0
	.global	_I2CADR_1
	.global	_I2CADR_2
	.global	_I2CADR_3
	.global	_I2CADR_4
	.global	_I2CADR_5
	.global	_I2CADR_6
